EP1AGX35CF484I6

EP1AGX35CF484I6 FPGAs Overview

The Arria GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria GX EP1AGX35CF484I6 devices include 4 to 12 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with the ability to develop proprietary, serial-based IP using its Basic mode. The transceivers build upon the success of the Stratix II GX family. The Arria GX FPGA technology offers a 1.2-V logic array with the right level of performance and dependability needed to support these mainstream protocols.

Arria GX EP1AGX35CF484I6 devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix II GX device family.

Arria GX EP1AGX35CF484I6 transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks located on the right side of the device. The transceiver blocks can be configured to support the following serial connectivity protocols (functional modes):    

■ PCI Express (PIPE)

■ Gigabit Ethernet (GIGE)

■ XAUI

■ Basic (600 Mbps to 3.125 Gbps)

■ SDI (HD, 3G)

■ Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)

The INTEL Programmable Logic ICs series EP1AGX35CF484I6 is Arria GX FPGAs—Risk-Free Connections to High-Speed Serial Devices; 484 pin FBGA; -40 to 100°C, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

Transceivers within each block are independent and have their own set of dividers. Therefore, each transceiver can operate at different frequencies.

Each block can select from two reference clocks to provide two clock domains that each transceiver can select from.

The key features of Arria GX devices include:

■ Transceiver block features

■ High-speed serial transceiver channels with CDR support up to 3.125 Gbps.

■ Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels

■ Support for the following CDR-based bus standards—PCI Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode

■ Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation

■ 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers

■ Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode)

■ Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices

■ Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial Digital Interface (SDI), and Serial RapidIO

■ 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding

■ Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array

■ Channel aligner compliant with XAUI

■ Main device features:

■ TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 380 MHz

■ Up to 16 global clock networks with up to 32 regional clock networks per device

■ High-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters

■ Up to four enhanced phase-locked loops (PLLs) per device provide spread spectrum, programmable bandwidth, clock switch-over, and advanced multiplication and phase shifting

■ Support for numerous single-ended and differential I/O standards

■ High-speed source-synchronous differential I/O support on up to 47 channels

■ Support for source-synchronous bus standards, including SPI-4 Phase 2

(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1

■ Support for high-speed external memory including DDR and DDR2 SDRAM, and SDR SDRAM

■ Support for multiple intellectual property megafunctions from Altera MegaCore functions and Altera Megafunction Partners Program (AMPPSM)

■ Support for remote configuration updates