EP1AGX60CF484I6N

EP1AGX60CF484I6N FPGAs Overview

The Arria GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria GX EP1AGX60CF484I6N devices include 4 to 12 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with the ability to develop proprietary, serial-based IP using its Basic mode. The transceivers build upon the success of the Stratix II GX family. The Arria GX FPGA technology offers a 1.2-V logic array with the right level of performance and dependability needed to support these mainstream protocols.

Arria GX EP1AGX60CF484I6N devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix II GX device family.

Arria GX EP1AGX60CF484I6N transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks located on the right side of the device. The transceiver blocks can be configured to support the following serial connectivity protocols (functional modes):    

■ PCI Express (PIPE)

■ Gigabit Ethernet (GIGE)

■ XAUI

■ Basic (600 Mbps to 3.125 Gbps)

■ SDI (HD, 3G)

■ Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)

The INTEL FPGA - Field Programmable Gate Array series EP1AGX60CF484I6N is FPGA - Field Programmable Gate Array FPGA - Arria GX 3005 LABs 229 IOs, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

Transceivers within each block are independent and have their own set of dividers. Therefore, each transceiver can operate at different frequencies.

Each block can select from two reference clocks to provide two clock domains that each transceiver can select from.

The key features of Arria GX devices include:

■ Transceiver block features

■ High-speed serial transceiver channels with CDR support up to 3.125 Gbps.

■ Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels

■ Support for the following CDR-based bus standards—PCI Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode

■ Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation

■ 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers

■ Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode)

■ Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices

■ Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial Digital Interface (SDI), and Serial RapidIO

■ 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding

■ Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array

■ Channel aligner compliant with XAUI

■ Main device features:

■ TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 380 MHz

■ Up to 16 global clock networks with up to 32 regional clock networks per device

■ High-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters