EP20K1000CF672C9ES

EP20K1000CF672C9ES FPGAs Overview

The EP20K1000CF672C9ES devices offer the MultiCore architecture, which combines the strengths of LUT-based and product-term-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for datapath, register-intensive, mathematical, or digital signal processing (DSP) designs. Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. LUT- and productterm-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the EP20K1000CF672C9ES architecture uniquely suited for SOPC designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one EP20K1000CF672C9ES device.

The EP20K1000CF672C9ES and EP20K1000E, members of the APEX 20K device family, provide 39,100 registers; 327,680 memory bits; and 1,000,000 typical gates. These devices are suitable for memory functions and complex logic functions such as digital signal processing, wide data-path manipulation, data transformation, and microcontrollers. The high-pin-count EP20K1000CF672C9ES and EP20K1000E devices contain an embedded array to implement memory functions and a logic array to implement general logic functions. You can integrate entire systems, including 32-bit buses, into a single EP20K1000CF672C9ES or EP20K1000E device. These devices meet the low-voltage requirements of 1.8-V applications and support multiple low-voltage I/O standards.

The Altera Embedded - FPGAs (Field Programmable Gate Array) series EP20K1000CF672C9ES is IC FPGA 508 I/O 672FBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

■ Programmable logic device (PLD) manufactured using a 0.15-µm alllayer copper-metal fabrication process

– 25 to 35% faster design performance than APEXTM 20KE devices

– Pin-compatible with APEX 20KE devices

– High-performance, low-power copper interconnect

– MultiCoreTM architecture integrating look-up table (LUT) logic and embedded memory

– LUT logic used for register-intensive functions

– Embedded system blocks (ESBs) used to implement memory

functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)

■ High-density architecture

– 200,000 to 1 million typical gates (see Table 1)

– Up to 38,400 logic elements (LEs)

– Up to 327,680 RAM bits that can be used without reducing available logic