EP2C50F484C8N

EP2C50F484C8N FPGAs Overview

Functional

 Cyclonee I devices contain a two-dimensional row-and column-basedDescrintion arhitecture toimplement custom losic. Column androw interconnects of varying speeds provide signal interconnects between logic array blocks(LABs), embedded memory blocks, and embedded multipliers.

The logic array consists of LABs, with 16 logic elements(LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone II devices range in density from 4,608 to 68,416LEs.
Cyclone II devices provide a global clock network and up to four phase-locked loops(PLLs). The global clock network consists of up to 16
global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as input/output elements(IOEs), LEs, embedded multipliers, and embedded memory blocks. The global clock lines can also be used forother high fan-out signals. Cyclone IⅡ PLLs provide general-purpose clocking with clock synthesis and phase shifting as well as external outputs for high-speed differential I/O support.
M4K memory blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 260 MHz. These blocks are arranged in columns across the device in between certain LABs. Cyclone II devices offer between 119 to1,152 Kbits of embedded memory.
Each embedded multiplier block can implement up to either two9×9-bit multipliers, or one 18× 18-bit multiplier with up to 250-MHz performance. Embedded multipliers are arranged in columns across the device.
Each Cyclone II device I/O pin is fed by an IOE located at the ends ofLAB rows and columns around the periphery of the device.I/O pins support various single-ended and differential I/O standards, such as the 66-and 33-MHz,64-and 32-bit PCI standard, PCI-X, and the LVDS I/O standard at a maximum data rate of 805 megabits per second(Mbps) for inputs and 640Mbps for outputs. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals.
Dual-purpose DQS, DQ, and DM pins along with delay chains(used tophase-align double data rate(DDR) signals) provide interface support for external memory devices such as DDR, DDR2, and single data rate(SDR)
SDRAM, and QDRII SRAM devices at up to 167 MHz.
Figure 2-1 shows a diagram of the Cyclone lⅡ EP2C20 device.
The INTEL Programmable Logic ICs series EP2C50F484C8N is FPGA, CYCLONE II, 50K LE, 484FBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

The Cyclone II device family offers the following features:

■ High-density architecture with 4,608 to 68,416 LEs

● M4K embedded memory blocks

● Up to 1.1 Mbits of RAM available without reducing available logic

● 4,096 memory bits per block (4,608 bits per block including 512 parity bits)

● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36

● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes

● Byte enables for data input masking during writes

● Up to 260-MHz operation

■ Embedded multipliers

● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance

● Optional input and output registers