EP610DC-30

EP610DC-30 FPGAs Overview

·High-Density（Over 600 Gates）
Replacement for TTL and 74HC
·Virtually Zero Standby Power...Typ 20 uA
·High Speed：Propagation Delay Time...25 ns
·Asynchronous Clocking of All Registers or Banked Register Operation from
2Synchronous Clocks
·Sixteen Macrocells with Configurable I/OArchitecture Allowing for Up to 20 Inputs and 16 Outputs Each Output Macrocell User-Programmable for D，T，SR，or JK Flip-Flops with Individual Clear Control or Combinational OperationUV-Light-Erasable Cell Technology Allows for：
-Reconfigurable Logic一Reprogrammable Cells
-Full Factory Testing for 100%

Programming Yields Programmable Design Security Bit Prevents Copying of Logic Stored in Device Advanced Software Support Featuring Schematic Capture，Interactive Netlist，Boolean Equations，and State Machine Design Entry

·Programmable Design Security Bit Prevents Copying of Logic Stored in Device
·Advanced Software Support Featuring Schematic Capture,Interactive Netlist, Boolean Equations,and State Machine Design Entry
·Package Options Include Plastic tfor One-
Time-Programmable (OTP)Devices] and Ceramic Dual-In-Line Packages and Chip Carriers

The Altera Memory chips series EP610DC-30 is DIP24 Simple EPLD, Programmable Array Logic, 24 Pin, Ceramic 91+, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

■ High-performance, 16-macrocell Classic EPLD – Combinatorial speeds withtPD as fast as 10 ns

– Counter frequencies of up to 100 MHz
– Pipelined data rates of up to 125 MHz
■ Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins
■ EP610 and EP610I devices are pin-, function-, and programming file-compatible
■ Programmable clock option for independent clocking of all registers
■ Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation
■ Available in the following packages (see Figure 7):
– 24-pin small-outline integrated circuit (plastic SOIC only)
– 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP)
– 28-pin plastic J-lead chip carrier (PLCC)