EPF6010ATC100-2

EPF6010ATC100-2 FPGAs Overview

The Altera FLEX 6000 EPF6010ATC100-2 programmable logic device (PLD) provides a low-cost alternative to high-volume gate array designs. FLEX 6000 devices are based on the OptiFLEX architecture, which minimizes die size while maintaining high performance and routability. The devices have reconfigurable SRAM elements, which give designers the flexibility to quickly change their designs during prototyping and design testing. Designers can also change functionality during operation via in-circuit reconfiguration.

FLEX 6000 EPF6010ATC100-2 devices are reprogrammable, and they are 100% tested prior to shipment. As a result, designers are not required to generate test vectors for fault coverage purposes, allowing them to focus on simulation and design verification. In addition, the designer does not need to manage inventories of different gate array designs. FLEX EPF6010ATC100-2 devices are configured on the board for the specific functionality required.

The INTEL FPGA - Field Programmable Gate Array series EPF6010ATC100-2 is FLEX 6000 Programmable Logic Device Family; 100 pin TQFP; 0 to 85°C, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

■ Provides an ideal low-cost, programmable alternative to highvolume gate array applications and allows fast design changes

during prototyping or design testing

■ Product features

– Register-rich, look-up table- (LUT-) based architecture

– OptiFLEX architecture that increases device area efficiency

– Typical gates ranging from 5,000 to 24,000 gates (see Table 1)

– Built-in low-skew clock distribution tree

– 100% functional testing of all devices; test vectors or scan chains

are not required

■ System-level features

– In-circuit reconfigurability (ICR) via external configuration

device or intelligent controller

– 5.0-V devices are fully compliant with peripheral component

interconnect Special Interest Group (PCI SIG) PCI Local Bus

Specification, Revision 2.2

– Built-in Joint Test Action Group (JTAG) boundary-scan test

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available

without consuming additional device logic

– MultiVoltTM I/O interface operation, allowing a device to bridge

between systems operating at different voltages

– Low power consumption (typical specification less than 0.5 mA

in standby mode)

– 3.3-V devices support hot-socketing