LC4064ZC-75TN48C FPGAs Overview
LC4064ZC-75TN48C Lattice Semiconductor Corporation, IC CPLD 64MC 7.5NS 48TQFP
CPLD ispMACH? 4000Z Family 64 Macro Cells 168MHz 1.8V 48-Pin TQFP
CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
The Lattice CPLD - Complex Programmable Logic Devices series LC4064ZC-75TN48C is MACH4000 ISP CPLD, TQFP48, 1.8V; Logic IC family:Programmable; Logic IC Base Number:4064Z; Logic IC function:Programmable CPLD; Voltage, supply:1.8V; Case style:TQFP / 48; Base number:4064; I/O lines, No. of:32; Logic function RoHS Compliant: Yes,CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
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Features
■ High Performance
• fMAX = 400MHz maximum operating frequency
• tPD = 2.5ns
propagation delay
• Up to four global clock pins with programmable clock
polarity control
• Up to 80 PTs per output
■ Ease of Design
• Enhanced
macrocells with individual clock, reset, preset and clock enable controls
• Up
to four global OE controls
• Individual local OE control per I/O pin
• Excellent
First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT path
•
Wide input gating (36 input logic blocks) for fast counters, state machines and
address decoders
■ Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)
• Typical static current 10µA (4032Z)
• Typical static current 1.3mA (4000C)
•
1.8V core low dynamic power
• ispMACH 4000Z operational down to 1.6V VCC
■ Broad Device Offering
• Multiple temperature range support
– Commercial: 0
to 90°C junction (Tj )
– Industrial: -40 to 105°C junction (Tj )
– Extended: -40
to 130°C junction (Tj )
• For AEC-Q100 compliant devices, refer to LA-ispMACH
4000V/Z Automotive Data Sheet
■ Easy System Integration
• Superior solution for
power sensitive consumer applications
• Operation with 3.3V, 2.5V or 1.8V LVCMOS
I/O
• Operation with 3.3V (4000V), 2.5V (4000B) or 1.8V (4000C/Z) supplies
• 5V
tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
• Hot-socketing
•
Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable
output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
•
3.3V/2.5V/1.8V In-System Programmable (ISP) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free package options