LFE2M70E-7FN1152C FPGAs Overview
Lattice's��LatticeECP2��� and��LatticeECP2M��� families of��field programmable gate arrays��(FPGAs) integrate high-performance��FPGAfeatures in a low cost device. The��ECP2��family features high-performance DSP blocks, up to 70K LUT capacity, support for DDR2 memory interfaces at 533Mbps and up to 840Mbps generic LVDS performance. The��ECP2M��offers embedded SERDES, 100K LUT, and memory capacity up to 5.3Mbits.
The Lattice Programmable Logic ICs series LFE2M70E-7FN1152C is FPGA - Field Programmable Gate Array 67K LUTs 430 I/O Memry DSP 1.2V -7Spd, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
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Features
■ High Logic Density for System Integration
• 6K to 95K LUTs
• 90 to
583 I/Os
■ Embedded SERDES (LatticeECP2M Only)
• Data Rates 250 Mbps to 3.125
Gbps
• Up to 16 channels per device PCI Express, Ethernet (1GbE, SGMII), OBSAI,
CPRI and Serial RapidIO.
■ sysDSP Block
• 3 to 42 blocks for high performance
multiply and accumulate
• Each block supports – One 36x36, four 18X18 or eight
9X9 multipliers
■ Flexible Memory Resources
• 55Kbits to 5308Kbits sysMEM
Embedded Block RAM (EBR)
– 18Kbit block
– Single, pseudo dual and true dual port
– Byte Enable Mode support
• 12K to 202Kbits distributed RAM
– Single port and
pseudo dual port
■ sysCLOCK Analog PLLs and DLLs
• Two GPLLs and up to six SPLLs
per device
– Clock multiply, divide, phase & delay adjust
– Dynamic PLL
adjustment
• Two general purpose DLLs per device
■ Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
•
Dedicated gearing logic
• Source synchronous standards support
– SPI4.2, SFI4
(DDR Mode), XGMII
– High Speed ADC/DAC devices
• Dedicated DDR and DDR2 memory
support
– DDR1: 400 (200MHz) / DDR2: 533 (266MHz)
• Dedicated DQS support
■
Programmable sysI/O Buffer Supports Wide Range Of Interfaces
• LVTTL and LVCMOS
33/25/18/15/12
• SSTL 3/2/18 I, II
• HSTL15 I and HSTL18 I, II
• PCI and
Differential HSTL, SSTL
• LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
■ Flexible Device
Configuration
• 1149.1 Boundary Scan compliant
• Dedicated bank for
configuration I/Os
• SPI boot flash interface
• Dual boot images supported
•
TransFR I/O for simple field updates
• Soft Error Detect macro embedded
■
Optional Bitstream Encryption (LatticeECP2/M “S” Versions Only)
■ System Level
Support
• ispTRACY internal logic analyzer capability
• On-chip oscillator for
initialization & general use
• 1.2V power supply