PALCE610H-20/BLA FPGAs Overview
The PALCE610H-20/BLA s a genera purpose PAL devce and is functicna y and fuse rap equivalent to the EP610. t can accommodate ogic 布nations w th up to 20 inputs anc If outputs Piece are 16 I/O macrccellsihat can be nc vidua y configured tc the user^s specifications. The macrocs can be configured as either registered or combinatorial. The registers be conf ^jred as D. T. J-K.crS-R flip-fops.
The PALCEQIOuses the familiar sunxi^jrocuots cgtz with programmable-AND and fixd-OR structure. Eght product terns are brought to each m*orccell io provide kcgc mplementaions.
The PALCE610H-20/BLA is r^nuUctured using acv^nced CMOS EE technolcfly praviding kw power consumption. Moreover, t is a hgh-speec dwce hav ng awctst- casetPDOf 15 m. Spa^-saving 24-pin SKINNYDIP and 26-pnPLCC packages are cffered.
This cevice m b« qu ckty erased and reproyanmed providing for e^sy prciotyping Onoe a devce is pro- Qrammed the security bit can be usee s provide protection from copying a propneury design.
The Lattice PALCE610 Family series PALCE610H-20/BLA is UV-Erasable/OTP PLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
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Features
■ Lattice/Vantis Programmable Array Logic (PAL) architecture
■ Electricalty-erasable CMOS technology providing half power (90 mAIcc) at high speed
— -15= 15-ns tpo
— -25=25-ns tpo
■ Sixteen macrocells with configurable I/O architecture
. Registered or combinatorial operation
■ Registers programmable as D. T. J-K. or S-R
■ ■ Asynchronous clocking via product term or bank register clocking from external pins
■ Register preload for testability
■ Power-up reset for initialization
■ ■ Space-saving 24-pin SKINNYD1P and 28-pin PLCC packages
■ ■ Fully tested for 100% programming yield and high reliability
■ ■ Extensive third-party software and programmer support through FusionPLD partners