Manufacturer | Xilinx® |
Series | Virtex®-5 LXT |
Manufacturer | Xilinx® |
Numberof I/ O | 360 |
Package / Case | 665-BBGA, FCBGA |
Product Status | Active |
Voltage- Supply | 0.95V ~ 1.05V |
Total R A M Bits | 1327104 |
Operating Temperature | -40°C ~ 100°C (TJ) |
Numberof L A Bs/ C L Bs | 2400 |
Integrated Circuits (ICs) | Embedded - FPGAs (Field Programmable Gate Array) |
Numberof Logic Elements/ Cells | 30720 |
Using the second generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the XC5VLX30T-1FFG665I contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, XC5VLX30T-1FFG665I FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO technology with built-in digitally-controlled impedance, ChipSync source-synchronous interface blocks, system monitor functionality,
The Xilinx FPGAs (Field Programmable Gate Array) series XC5VLX30T-1FFG665I is FPGA Virtex-5 LXT Family 30720 Cells 65nm (CMOS) Technology 1V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.Most advanced, high-performance, optimal-utilization, FPGA fabric
Real 6-input look-up table (LUT) technology
Dual 5-LUT option
Improved reduced-hop routing
64-bit distributed RAM option
SRL32/Dual SRL16 option
Powerful clock management tile (CMT) clocking
Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting
PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
36-Kbit block RAM/FIFOs
True dual-port widths up to x36
Simple dual-port widths up to x72
True dual-port RAM blocks
Enhanced optional programmable FIFO logic
Programmable
Built-in optional error-correction circuitry
Optionally program each block as two independent 18-Kbit blocks
High-performance parallel SelectIO technology
System Monitoring capability on all devices
Integrated Endpoint blocks for PCI Express Designs
Tri-mode 10/100/1000 Mb/s Ethernet MACs
RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
LXT and SXT Platforms
RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
TXT and FXT Platforms
PowerPC 440 Microprocessors
FXT Platform only
RISC architecture
7-stage pipeline
32-Kbyte instruction and data caches included
Optimized processor interface structure (crossbar)
65-nm copper CMOS process technology