AGLE600V2-FGG484

AGLE600V2-FGG484 FPGAs Overview

The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features.

The Flash*Freeze technology used in IGLOOe devices enables entering and exiting an ultra-lowpower mode while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption while the IGLOOe device is completely functional in the system. This allows the IGLOOe device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power.

Nonvolatile flash technology gives IGLOOe devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). IGLOOe is reprogrammable and offers time-tomarket benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.

The Actel FPGA - Field Programmable Gate Array series AGLE600V2-FGG484 is FPGA IGLOOe Family 600K Gates 526.32MHz/892.86MHz 130nm Technology 1.2V/1.5V 484-Pin FBGA Tray, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• Low-Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content
• Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-LowPower Flash*Freeze Mode
High Capacity
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization