EP1S30F780C7N FPGAs Overview
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Information
This handbook provides comprehensive information about the Alterae Stratix family of devices.
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Features
Stratix devices are available in space-saving FineLine BGA® and ball-grid array (BGA) packages (see Tables 1–3 through 1–5). All Stratix devices support vertical migration within the same package (for example, you can migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672-pin BGA package).
Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the
same for a given package across device densities. For I/O pin migration across densities, you must cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins are migrational. The Quartus® II software can
automatically cross reference and place all pins except differential pins for migration when given a device migration list. You must use the pinouts for each device to verify the differential placement migration. A future version of the Quartus II software will support differential pin migration.
Stratixe devices contain a two-dimensional row-and column-based architecture to implement custom logic.A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks.
The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz.M512 blocks are grouped into columns across the device in between certain LABs.
M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity(4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291MHz.
These blocks are grouped into columns across the device in between certain LABs.
M-RAM blocks are true dual-port memory blocks with 512K bits plus parity(589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to
269MHz. Several M-RAM blocks are located individually or in pairs within the device's logic array.
Digital signal processing(DSP) blocks can implement up to either eight full-precision 9× 9-bit multipliers, four full-precision 18× 18-bit multipliers, or one full-precision 36× 36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for digital signal processing applications, including FIR and infinite impulse response(IR) filters. DSP blocks are grouped into two columns in each device.
Each Stratix device I/O pin is fed by an I/O element 1OE) located at the end of LAB rows and columns around the periphery of the device.I/Opins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional 1/O buffer and six registers for registering input, output, and output-enable signals. When used with
The INTEL Embedded - FPGAs (Field Programmable Gate Array) series EP1S30F780C7N is FPGA Stratix Family 32470 Cells 420.17MHz 130nm Technology 1.5V 780-Pin FC-FBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
and you can also search for other FPGAs products.
Features
EPC devices offer the following features:
■ Single-chip configuration solution for Altera ACEX 1K, APEX 20K
(including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone,
Cyclone II, FLEX
10K (including FLEX 10KE and FLEX 10KA), Mercury, Stratix II, and Stratix
II GX devices
■ Contains 4-, 8-, and 16-Mb flash memories for configuration data
storage
■ On-chip decompression feature almost doubles the effective configuration
density
■ Standard flash die and a controller die combined into single stacked chip
package
■ External flash interface supports parallel programming of flash and
external processor access to unused portions of memory
■ Flash memory block or sector protection capability using the external flash
interface
■ Supported in EPC4 and EPC16 devices