EP20K100EQC208-3 FPGAs Overview
General
Description
APEXTM 20K devices are the first PLDs designed with the MultiCore
architecture, which combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic
provides optimized performance and efficiency for data-path, registerintensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths,
such as complex state machines. LUT- and product-term-based logic
combined with memory functions and a wide variety of MegaCore and
AMPP functions make the APEX 20K device architecture uniquely suited
for system-on-a-programmable-chip designs. Applications historically
requiring a combination of LUT-, product-term-, and memory-based
devices can now be integrated into one APEX 20K device.
Features
■ Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration
– MultiCoreTM architecture integrating look-up table (LUT) logic,product-term logic, and embedded memory
– LUT logic used for register-intensive functions
– Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)
– ESB implementation of product-term logic used for combinatorial-intensive functions
■ High density
– 30,000 to 1.5 million typical gates (see Tables 1 and 2)
– Up to 51,840 logic elements (LEs)
– Up to 442,368 RAM bits that can be used without reducing available logic
– Up to 3,456 product-term-based macrocells
The INTEL Embedded - FPGAs (Field Programmable Gate Array) series EP20K100EQC208-3 is FPGA APEX 20K Family 100K Gates 4160 Cells 250MHz 0.22um Technology 1.8V 208Pin PQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
and you can also search for other FPGAs products.
Features
■ Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
– MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
– LUT logic used for register-intensive functions
– Embedded system block (ESB) used to implement memory functions, including
first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory
(CAM)
– ESB implementation of product-term logic used for combinatorial-intensive
functions
■ Designed for low-power operation
– 1.8-V and 2.5-V supply voltage
– MultiVoltTM I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices
– ESB offering programmable power-saving mode