EP2S60F1020I4N

EP2S60F1020I4N FPGAs Overview

Introduction

 The stratix@ I FPGA family is based on a 1.2-V,90nm, alllayer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements(LEs). Stratix IⅡ devices offer up to 9 Mbits of on-chip, TriMatrixTM memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384(18-bit x 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions. Various high-speed external memory interfaces are supported, including double data rate(DDR) SDRAM and DDR2 SDRAM, RLDRAM II, quad data rate (QDR)IⅡ SRAM, and single data rate(SDR) SDRAM. Stratix II devices support various I/O standards along with support for 1-gigabit per second(Gbps) source synchronous signaling with DPA circuitry. Stratix II devices offer a complete clock management solution with internal clock frequency of up to 550 MHz and up to 12 phase-locked loops(PLLs). Stratix II devices are also the industry's first FPGAs with the ability to decrypt a configurationbitstream using the Advanced Encryption Standard (AES) algorithm to protect designs.

Features

TheStratixlIl family offers the following features:
■15,600 to 179,400 equivalent LEs;see Table1-1
■New and innovative adaptive logic module(ALM),the basic building block of the Stratix Il architecture,maximizes performance and resource usage efficiency
■Up to 9,383,040 RAM bits(1,172,880 bytes) available without reducing logic resources
■TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out(FIFO)buffers
■High-speed DSP blocks provide dedicated implementation of multipliers(at up to 450 MHz),multiply-accumulate functions,and finite impulse response(FIR)filters
■Up to 16 global clocks with 24 clocking resources per device region Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
■Up to 12 PLLs(four enhanced PLLs and eight fast PLLs)per device provide spread spectrum,programmable bandwidth,clock switch-over,real-time PLL reconfiguration,and advanced multiplication and phase shifting

■Support for numerous single-ended and differential I/O standards
■High-speed differential I/O support with DPA circuitry for 1-Gbps performance
■Support for high-speed networking and communications bus standards including Parallel RapidlO,SPI-4 Phase 2(POS-PHY Level 4),Hyper TransportTM technology,and SFl-4
■Support for high-speed external memory,including DDR and DDR2 SDRAM,RLDRAM Ⅱ,QDR I SRAM,and SDR SDRAM
■ Support for multiple intellectual property megafunctions from Altera MegaCore? functions and Altera Megafunction Partners Program(AMPPSM) megafunctions
■Support for design security using configuration bitstream encryption
■Support for remote configuration updates

Functional

 stratixce n devices contain a two-dimensional row-and column-based architecture to implement custom logic.A series of column and row Description inteconects of varying length and speed provides signal interconnects between logic array blocks(LABs), memory block structures(M512RAM, M4K RAM, and M-RAM blocks), and digital signal processing(DSP)
blocks.
Each LAB consists of eight adaptive logic modules(ALMs). An ALM is the Stratix II device family's basic building block of logic providingefficient implementation of user logic functions. LABs are grouped into rows and columns across the device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 500 MHz.M512 blocks are grouped into columns across the device in between certain LABs.
M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 550 MHz.
These blocks are grouped into columns across the device in between certain LABs.
M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to
420MHz. Several M-RAM blocks are located individually in the device's logic array.
DSP blocks can implement up to either eight full-precision9×9-bit multipliers, four full-precision 18x 18-bit multipliers, or one full-precision 36×36-bit multiplier with add or subtract features. The DSP blocks support Q1.15 format rounding and saturation in the multiplier and accumulator stages. These blocks also contain shift registers for digital signal processing applications, including finite impulse response(FIR) and infinite impulse response(IIR) filters. DSP blocks are grouped into columns across the device and operate at up to
450MHz.

The INTEL Embedded - FPGAs (Field Programmable Gate Array) series EP2S60F1020I4N is FPGA Stratix II Family 60440 Cells 711.24MHz 90nm (CMOS) Technology 1.2V 1020Pin FC-FBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

The Stratix II family offers the following features:

■ New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency

■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources

■ TriMatrixmemory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers

■ High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters

■ Up to 16 global clocks with 24 clocking resources per device region

■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode

■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting