ICE40LP1K-SWG16-EVN FPGAs Overview
Now you can create ingenious mobile products while staying well within your cost, power, size and schedule targets. Lattice's iCE40 devices allow instant innovation by customizing solutions based on off-the-shelf chips; which means maximum product differentiation with minimum cost and effort. Available in three series: Low power (LP), low power with embedded IP (LM) and high performance (HX). The iCE40 FPGAs can be used in countless ways to add differentiation to mobile products. Shown below are four of the most common iCE40 design categories along with specific application examples. Enhance application processor connectivity Provide additional GPIOs to extend the processor's interface capabilities Translate voltages to overcome limitations in the supported voltage standards Increase performance by aggregating multiple slow serial buses onto high-speed links Increase battery life by offloading timing critical functions Accurately send and receive data with IR LEDs and photodiodes for remote communication Communicate via slow UART and I²C interfaces while the microprocessor is asleep Capture all user inputs by buffering sensor data and generating smart interrupts Increase system performance through hardware acceleration Reduce processor workload by pre-processing sensor data to generate nine-axis output Rotate, combine and scale image data with efficient FPGA-based implementations Use logic-based multipliers to implement high-performance digital signal filtering Select the ideal components for your design using flexible interface bridging Match your preferred display to your application processor with interfaces such as RGB, 7:1 LVDS and MIPI DPI/DBI Multi-source your image sensors by implementing flexible bridges supporting common interfaces such as HiSPi, subLVDS, LVDS, and Parallel LVCMOS Bridge the latest MIPI Battery Interface (BIF) to existing interfaces such as I²C
The Lattice Programmers, Development Systems series ICE40LP1K-SWG16-EVN is iCE40LP1K-SWG16 FPGA Evaluation Kit 27MHz CPU SPI Flash, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
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Features
Flexible Logic Architecture
• Five devices with 384 to 7,680 LUT4s and 10 to 206 I/Os
Ultra Low Power Devices
• Advanced 40 nm low power process
• As low as 21 µA standby power
• Programmable low swing differential I/Os
Embedded and Distributed Memory
• Up to 128 kbits sysMEM Embedded Block RAM
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
High Current LED Drivers
• Three High Current Drivers used for three different LEDs or one RGB LED
High Performance, Flexible I/O Buffer
• Programmable sysIO buffer supports wide range of interfaces:
— LVCMOS 3.3/2.5/1.8
— LVDS25E, subLVDS
— Schmitt trigger inputs, to 200 mV typical hysteresis
• Programmable pull-up mode
Flexible On-Chip Clocking
• Eight low-skew global clock resources
• Up to two analog PLLs per device
Flexible Device Configuration
• SRAM is configured through:
— Standard SPI Interface
— Internal Nonvolatile Configuration Memory (NVCM)
Broad Range of Package Options
• WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options
• Small footprint package options
— As small as 1.40 mm x 1.48 mm
• Advanced halogen-free packaging