ICE40LP1K-SWG16TR

The iCE40 family of ultra-low power, non-volatile FPGAs has five devices with densities ranging from 384 to 7680 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features allow the devices to be used in low-cost, high-volume consumer and system applications. Select packages offer High-Current drivers that are ideal to drive three white LEDs, or one RGB LED. The iCE40 devices are fabricated on a 40 nm CMOS low power process. The device architecture has several features such as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. These features help manage static and dynamic power consumption, resulting in low static power for all members of the family. The iCE40 devices are available in two versions – ultra low power (LP) and high performance (HX) devices.

The iCE40 FPGAs are available in a broad range of advanced halogen-free packages ranging from the space saving 1.40x1.48 mm WLCSP to the PCB-friendly 20x20 mm TQFP. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters. The iCE40 devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a

“per-pin” basis. The iCE40 devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash or be configured by an external master such as a CPU.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 family of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.

 Flexible Logic Architecture

• Five devices with 384 to 7,680 LUT4s and 10 to 206 I/Os

 Ultra Low Power Devices

• Advanced 40 nm low power process

• As low as 21 µA standby power

• Programmable low swing differential I/Os

 Embedded and Distributed Memory

• Up to 128 kbits sysMEM Embedded Block RAM

 Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

 High Current LED Drivers

• Three High Current Drivers used for three different LEDs or one RGB LED

 High Performance, Flexible I/O Buffer

• Programmable sysIO buffer supports wide range of interfaces:

— LVCMOS 3.3/2.5/1.8

— Schmitt trigger inputs, to 200 mV typical hysteresis

• Programmable pull-up mode

 Flexible On-Chip Clocking

• Eight low-skew global clock resources

• Up to two analog PLLs per device

 Flexible Device Configuration

• SRAM is configured through:

— Standard SPI Interface

— Internal Nonvolatile Configuration Memory (NVCM)

 Broad Range of Package Options

• WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options

• Small footprint package options

— As small as 1.40 mm x 1.48 mm

• Advanced halogen-free packaging