ISPGAL22LV10-4LK

ISPGAL22LV10-4LK FPGAs Overview

The ispGAL22LV10 is manufactured using Lattice Semiconductor's advanced 3.3V ECMOS process, which combines CMOS with Electrically Erasable(E2) floating gate technology. The ispGAL22LV10 can interface with both 3.3V and 5V signal levels.

The ispGAL22LV10 is fuly function/fuse map compatible with the GALQ22LV10 and GAL22V10. Further, the ispGAL22LV10 is parametric compatible with the GAL22LV10. The ispGAL22LV10 also shares the same 28-pin PLCC package pin-out as the GAL22LV10.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified.

The Lattice SPLD - Simple Programmable Logic Devices series ISPGAL22LV10-4LK is Electrically-Erasable PLD,SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

• IN-SYSTEM PROGRAMMABLE

— IEEE 1149.1 Standard TAP Controller Port Programming

— 4-Wire Serial Programming Interface

— Minimum 10,000 Program/Erase Cycles

• HIGH PERFORMANCE E2CMOS TECHNOLOGY

— 4 ns Maximum Propagation Delay

— Fmax = 250 MHz

— 3 ns Maximum from Clock Input to Data Output

— UltraMOS Advanced CMOS Technology

• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE

— JEDEC-Compatible 3.3V Interface Standard

— 5V Tolerant Inputs and I/O

— I/O Interfaces with Standard 5V TTL Devices

• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS

• COMPATIBLE WITH STANDARD 22LV10/22V10 DEVICES

— Function/Fuse-Map Compatible with 22LV10/22V10 Devices

— Parametric Compatible with 22LV10

• E2 CELL TECHNOLOGY

— In-System Programmable Logic

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention