ISPGAL22V10AB-5LJ FPGAs Overview
The ISPGAL22V10AB-5LJ is manufactured using Lattice
Semiconductor’s advanced E2
CMOS process, which
combines CMOS with Electrically Erasable (E2
) floating
gate technology. With an advanced E2
low-power cell
and full CMOS logic approach, the ISPGAL22V10AB-5LJ devices offers fast pin-to-pin speeds, while simultaneously
delivering low standby power without requiring any
“turbo bits” or other traditional power management
schemes. The ispGAL22V10A can interface with both
3.3V, 2.5V and 1.8V signal levels.
The ISPGAL22V10AB-5LJ is functionally compatible with the
ispGAL22LV10, GAL22LV10 and GAL22V10.
The Lattice Programmable Logic ICs series ISPGAL22V10AB-5LJ is SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
and you can also search for other FPGAs products.
Features
■ High Performance
• tPD = 2.3ns propagation delay
• fMAX = 455 MHz maximum operating frequency
• tCO = 2ns maximum from clock input to data output
• tSU = 1.3 ns clock set-up time
■ Low Power
• 1.8V core E2 CMOS technology
• Typical standby power <300µW (ispGAL22V10AC)
• CMOS design techniques provide low static and dynamic power
■ Space-Saving Packaging
• Available in 32-pin QFNS (Quad Flat-pack, No lead, Saw-singulated) package 5mm x 5mm body size1
■ Easy System Integration
• Operation with 3.3V (ispGAL22V10AV), 2.5V
(ispGAL22V10AB) or 1.8V (ispGAL22V10AC)supplies
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3 interface
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Lead-free package option
• Programmable output slew rate
• 3.3V PCI compatible
■ In-System Programmable
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V in-system programmable
(ISP) using IEEE 1532 compliant interface
■ E2 CELL TECHNOLOGY
• In-system programmable logic
• 100% tested/100% yields
• High speed electrical erasure (<50ms)