ISPLSI5384VA-70LB388I

ISPLSI5384VA-70LB388I FPGAs Overview

The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.

Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and five extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term.

The Lattice SuperWIDE High Density PLD series ISPLSI5384VA-70LB388I is CPLD ispLSI 5000VA Family 18K Gates 384 Macro Cells 70MHz 3.3V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

• SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC

— 3.3V Power Supply

— User Selectable 3.3V/2.5V I/O

— 18,000 PLD Gates / 384 Macrocells

— Up to 288 I/O Pins

— 384 Registers

— High-Speed Global Interconnect

— SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance

— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.

— PCB Efficient Ball Grid Array (BGA) Package Options

— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E2 CMOS TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay

— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns, tsu3 (CLK2/3) = 3.5ns

— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs

— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell

— Macrocells Support Concurrent Combinatorial and Registered Functions

— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable

— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks

— Slew and Skew Programmable I/O (SASPI/O) Supports Programmable Bus Hold, Pull-up, Open Drain and Slew and Skew Rate Options

— Six Global Output Enable Terms, Two Global OE Pins and One Product Term OE per Macrocell

• ispDesignEXPERT – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER

— PC and UNIX Platforms