ISPLSI8600V-60LB492

ISPLSI8600V-60LB492 FPGAs Overview

The ispLSI 8600V device has five Big Fast Megablocks for a total of 5 x 120 = 600 macrocells.

Each Big Fast Megablock has a total of 24 I/O cells and the Global Routing Plane has a total of 144 I/O cells. This gives (5 x 24) + 144 = 264 I/Os for the full I/O version, while the partial I/O version contains 72 BFM I/O + 120 Global I/O = 192 I/Os.

The total registers in the device is the sum of macrocells plus I/O cells, 600 + 264 = 864 registers.

Features

• SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC

— 3.3V Power Supply

— 32,000 PLD Gates/600 Macrocells

— 192-264 I/O Pins Supporting 3.3V/2.5V I/O

— 864 Registers

— High-Speed Global and Big Fast Megablock (BFM) Interconnect

— Wide 20-Macrocell Generic Logic Block (GLB) for High Performance

— Wide Input Gating (44 Inputs per GLB) for Fast Counters, State Machines, Address Decoders, Etc.

— PCB-Efficient Ball Grid Array (BGA) Package Options

• HIGH-PERFORMANCE E2 CMOS TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 8.5 ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture, Symmetrical Generic Logic Blocks Connected by Hierarchical Big Fast Megablock and Global Routing Planes

— Product Term Sharing Array Supports up to 28 Product Terms per Macrocell Output

— Macrocells Support Concurrent Combinatorial and Registered Functions

— Embedded Tristate Bus Can Be Used as an Internal Tristate Bus or as an Extension of an External Tristate Bus

— Macrocell and I/O Registers Feature Multiple Control Options, Including Set, Reset and Clock Enable

— I/O Pins Support Programmable Bus Hold, Pull-Up, Open-Drain and Slew Rate Options

— Separate VCCIO Power Supply to Support 3.3V or 2.5V Input/Output Logic Levels

— I/O Cell Register Programmable as Input Register for Fast Setup Time or Output Register for Fast Clock to Output Time

• ispDesignEXPERT

– LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER

— PC and UNIX Platforms