ISPPAC10-01PI FPGAs Overview
The ispPAC10 consists of four programmable analog macrocells called
PACblocks, each emulating a collection of operational amplifiers, resistors and
capacitors. Requiring no external components, it flexibly implements basic
analog functions such as precision filtering, summing/differencing,
gain/attenuation and integration. Each PACblock contains a summing amplifier,
two differential input instrument amplifiers, and an array of feedback
capacitors. The capacitors, combined with a fixed value feedback element,
provide more than 120 programmable poles between 10kHz to 100kHz with an
absolute accuracy of 5.0 percent. Variable gain input instrument amplifiers make
it possible to program any PACblock gain in integer steps between ±1 and ±10.
More complex signal processing functions are performed by configuring additional
PACblocks in combination with each other to achieve a variety of circuit
functions.
The ispPAC10 architecture is fully differential from input to output.
This effectively doubles dynamic range versus single-ended I/O. It also affords
improved performance with regard to specifications such as input common mode
rejection (CMR) and total harmonic distortion (THD).
Differential peak-peak
voltage is determined by knowing the signal extremes on both differential input
or output pins. For example, if V(+) equals 4V and V(-) equals 1V, the
differential voltage is defined as V(+) - V(-) = Vdiff, or 4V - 1V = +3V. Since
either polarity can exist on differential I/O pins, it is also possible for the
opposite extreme to exist and would mean when V(+) equals 1V and V(-) equals 4V,
the differential voltage is now 1V - 4V = -3V. To calculate the differential
peak-peak voltage or full signal swing, the absolute difference between the two
extreme Vdiff’s is calculated. Using the previous examples would result in
|(+3V) - (-3V)| = 6V. It can be immediately seen that true differential signals
result in a doubling of usable dynamic range. For more explanation of this and
other differential circuit benefits, please refer to application note AN6019.
Input polarity is programmable without affecting input impedance or dynamic
performance, since no internal change is made other than routing to the input
amplifier. Single-ended operation is achieved by using either one input and/or
one output pin, as required, and adjusting gain settings to achieve desired
output levels. The ispPAC10 operates on a single 5V supply and includes an
internal reference generating 2.5V. This reference is made available externally
through the voltage common-mode reference or VREFOUT pin (Pin 22). The output common mode
voltage is always referenced to 2.5V, regardless of the input common mode level.
It is possible, when desired, to use an externally supplied voltage instead of
VREFOUT, however. This optional common-mode output voltage (VCM) must be
provided by the user via the CMVIN input pin (Pin 19). The only limitation is
this reference voltage must be between 1.25V and 3.25V. When an external voltage
is present, an ispPAC10 must be programmed, on a per-PACblock basis, to use the
external reference instead of the internal 2.5V.
Configuring an ispPAC10 is
accomplished using PAC-Designer, a Windows-based design environment.
PAC-Designer includes an AC simulator for design verification prior to
programming. The user can download the design to the ispPAC10 at any time via
the device’s IEEE Standard 1149.1 (JTAG) compliant serial port directly from the
parallel port of a PC using an ispDOWNLOAD cable. Once downloaded, the circuit
topology and component values are stored in non-volatile digital E2CMOS cells on
the ispPAC10 without any need for external programming voltages.
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Features
• IN-SYSTEM PROGRAMMABLE (ISP) ANALOG CIRCUIT
— Four Instrument Amplifier
Gain/Attenuation Stages
— Signal Summation (Up to 4 Inputs)
— Precision Active
Filtering (10kHz to 100kHz)
— No External Components Needed for Configuration
—
Non-Volatile E2 CMOS Cells (10,000 Cycles)
— IEEE 1149.1 JTAG Serial Port
Programming
• FOUR LINEAR ELEMENT BUILDING BLOCKS
— Programmable Gain Range (0dB
to 80dB)
— Bandwidth of 550kHz (G=1), 330kHz (G=10)
— Low Distortion (THD <
-74dB max @ 10kHz)
— Auto-Calibrated Input Offset Voltage
• TRUE DIFFERENTIAL
I/O (±3V RANGE)
— High CMR (69dB) Instrument Amplifier Inputs
— 2.5V Common Mode
Reference on Chip
— Four Rail-to-Rail Voltage Outputs
• 28-PIN PLASTIC DIP OR
SOIC PACKAGE
— Single Supply 5V Operation