LC5512MB-75F256C FPGAs Overview
LC5512MB-75F256C Lattice Semiconductor Corporation, IC CPLD 512MC 7.5NS 256FBGA
IC CPLD 512MC 7.5NS 256FBGA
CPLD ispXPLD 5000MB Family 150K Gates 512 Macro Cells 150MHz 2.5V 256-Pin FBGA
CPLD - Complex Programmable Logic Devices PROGRAM EXPANDED LOG
The Lattice CPLD - Complex Programmable Logic Devices series LC5512MB-75F256C is CPLD ispXPLD 5000MB Family 150K Gates 512 Macro Cells 150MHz 2.5V 256-Pin FBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
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Features
■ Flexible Multi-Function Block (MFB) Architecture
• SuperWIDE logic (up to
136 inputs)
• Arithmetic capability
• Single- or Dual-port SRAM
• FIFO
• Ternary
CAM
■ sysCLOCK PLL Timing Control
• Multiply and divide between 1 and 32
•
Clock shifting capability
• External feedback capability
■ sysIO Interfaces
•
LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible
bus-maintenance (Pull-up, pulldown, bus-keeper, or none)
– Open drain operation
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI 3.3
• GTL+
• LVDS
• LVPECL
•
LVTTL
■ Expanded In-System Programmability (ispXP)
• Instant-on capability
•
Single chip convenience
• In-System Programmable via IEEE 1532 Interface
•
Infinitely reconfigurable via IEEE 1532 or sysCONFIG microprocessor interface
•
Design security
■ High Speed Operation
• 4.0ns pin-to-pin delays, 300MHz fMAX
•
Deterministic timing
■ Low Power Consumption
• Typical static power: 20 to 50mA
(1.8V), 30 to 60mA (2.5/3.3V)
• 1.8V core for low dynamic power
■ Easy System
Integration
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V (5000MC) power supply
operation
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces
• IEEE 1149.1
interface for boundary scan testing
• sysIO quick configuration
• Density
migration
• Multiple density and package options
• PQFP and fine pitch BGA
packaging
• Lead-free package options