LFE3-95EA-SP-EVN FPGAs Overview
The LatticeECP3 (EConomy Plus Third generation) family of FPGA devices is
optimized to deliver high performance features such as an enhanced DSP
architecture, high speed SERDES and high speed source synchronous interfaces in
an economical FPGA fabric. This combination is achieved through advances in
device architecture and the use of 65 nm technology making the devices suitable
for high-volume, high-speed, low-cost applications.
The LatticeECP3 device
family expands look-up-table (LUT) capacity to 149K logic elements and supports
up to 586 user I/Os. The LatticeECP3 device family also offers up to 320 18 x 18
multipliers and a wide range of parallel I/O standards.
The LatticeECP3 FPGA
fabric is optimized with high performance and low cost in mind. The LatticeECP3
devices utilize reconfigurable SRAM logic technology and provide popular
building blocks such as LUT-based logic, distributed and embedded memory, Phase
Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source
synchronous I/O support, enhanced sysDSP slices and advanced configuration
support, including encryption and dual-boot capabilities.
The pre-engineered
source synchronous logic implemented in the LatticeECP3 device family supports a
broad range of interface standards, including DDR3, XGMII and 7:1 LVDS.
The
LatticeECP3 device family also features high speed SERDES with dedicated PCS
functions. High jitter tolerance and low transmit jitter allow the SERDES plus
PCS blocks to be configured to support an array of popular data protocols
including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit
Pre-emphasis and Receive Equalization settings make the SERDES suitable for
transmission and reception over various forms of media.
The LatticeECP3 devices
also provide flexible, reliable and secure configuration options, such as
dual-boot capability, bit-stream encryption, and TransFR field upgrade features.
The Lattice Diamond and ispLEVER design software allows large complex designs
to be efficiently implemented using the LatticeECP3 FPGA family. Synthesis
library support for LatticeECP3 is available for popular logic synthesis tools.
Diamond and ispLEVER tools use the synthesis tool output along with the
constraints from its floor planning tools to place and route the design in the
LatticeECP3 device. The tools extract the timing from the routing and
back-annotate it into the design for timing verification.
Lattice provides many
pre-engineered IP (Intellectual Property) modules for the LatticeECP3 family. By
using these configurable soft core IPs as standardized blocks, designers are
free to concentrate on the unique aspects of their design, increasing their
productivity.
The Lattice Programmable Logic ICs series LFE3-95EA-SP-EVN is FPGA - Field Programmable Gate Array LatticeECP3-95EA Serial Protocol Brd, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
and you can also search for other FPGAs products.
Features
Higher Logic Density for Increased System Integration
• 17K to 149K LUTs
•
116 to 586 I/Os Embedded SERDES
• 150 Mbps to 3.2 Gbps for Generic 8b10b,
10-bit SERDES, and 8-bit SERDES modes
• Data Rates 230 Mbps to 3.2 Gbps per
channel for all other protocols
• Up to 16 channels per device: PCI Express,
SONET/SDH, Ethernet (1GbE, SGMII, XAUI), CPRI, SMPTE 3G and Serial RapidIO
sysDSP
• Fully cascadable slice architecture
• 12 to 160 slices for high
performance multiply and accumulate
• Powerful 54-bit ALU operations
• Time
Division Multiplexing MAC Sharing
• Rounding and truncation
• Each slice
supports
— Half 36x36, two 18x18 or four 9x9 multipliers
— Advanced 18x36 MAC
and 18x18 MultiplyMultiply-Accumulate (MMAC) operations
Flexible Memory
Resources
• Up to 6.85Mbits sysMEM Embedded Block RAM (EBR)
• 36K to 303K bits
distributed RAM
sysCLOCK Analog PLLs and DLLs
• Two DLLs and up to ten PLLs
per device
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O
cells
• Dedicated read/write levelling functionality
• Dedicated gearing logic
•
Source synchronous standards support
— ADC/DAC, 7:1 LVDS, XGMII
— High Speed
ADC/DAC devices
• Dedicated DDR/DDR2/DDR3 memory with DQS support
• Optional
Inter-Symbol Interference (ISI) correction on outputs
Programmable sysI/O
Buffer Supports Wide Range of Interfaces
• On-chip termination
• Optional
equalization filter on inputs
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL
33/25/18/15 I, II
• HSTL15 I and HSTL18 I, II
• PCI and Differential HSTL, SSTL
• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
Flexible Device Configuration
•
Dedicated bank for configuration I/Os
• SPI boot flash interface
• Dual-boot
images supported
• Slave SPI
• TransFR I/O for simple field updates
• Soft
Error Detect embedded macro
System Level Support
• IEEE 1149.1 and IEEE 1532
compliant
• Reveal Logic Analyzer
• ORCAstra FPGA configuration utility
•
On-chip oscillator for initialization & general use
• 1.2 V core power
supply