LFSCM3GA25EP1-7F900C FPGAs Overview
The LatticeSC family of FPGAs combines a high-performance FPGA fabric, high-speed SERDES, high-performance I/Os and large embedded RAM in a single industry leading architecture. This FPGA family is fabricated in a state of the art technology to provide one of the highest performing FPGAs in the industry. This family of devices includes features to meet the needs of today’s communication network systems. These features include SERDES with embedded advance PCS (Physical Coding sub-layer), up to 7.8 Mbits of sysMEM embedded block RAM, dedicated logic to support system level standards such as RAPIDIO, SPI4.2, SFI-4, UTOPIA, XGMII and CSIX.
Features
■ High Performance FPGA Fabric
• 15K to 115K four input Look-up
Tables (LUT4s)
• 139 to 942 I/Os
• 700MHz global clock; 1GHz edge clocks
■ 4 to
32 High Speed SERDES and flexiPCS (per Device)
• Performance ranging from
600Mbps to 3.8Gbps
• Excellent Rx jitter tolerance (0.8UI at 3.125Gbps)
• Low Tx
jitter (0.25UI typical at 3.125Gbps)
• Built-in Pre-emphasis and equalization
•
Low power (typically 105mW per channel)
• Embedded Physical Coding Sublayer
(PCS) provides pre-engineered implementation for the following standards:
– GbE,
XAUI, PCI Express, SONET, Serial RapidIO, 1G Fibre Channel, 2G Fibre Channel
■ 2Gbps High Performance PURESPEED I/O
• Supports the following performance
bandwidths
– Differential I/O up to 2Gbps DDR (1GHz Clock)
– Single-ended memory
interfaces up to 800Mbps
• 144 Tap programmable Input Delay (INDEL) block on
every I/O dynamically aligns data to clock for robust performance
– Dynamic bit
Adaptive Input Logic (AIL) monitoring and control circuitry per pin that
automatically ensures proper set-up and hold
– Dynamic bus: uses control bus
from DLL
– Static per bit
• Electrical standards supported:
– LVCMOS
3.3/2.5/1.8/1.5/1.2, LVTTL
– SSTL 3/2/18 I, II; HSTL 18/15 I, II
– PCI, PCI-X
–
LVDS, Mini-LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS, Hypertransport
• Programmable On
Die Termination (ODT)
– Includes Thevenin Equivalent and low power VTT
termination options
■ sysCLOCK Network
• Eight analog PLLs per device
– Frequency range from 15MHz to 1GHz
– Spread spectrum support
• 12 DLLs per device with direct control of I/O
delay
– Frequency range from 100MHz to 700MHz
• Extensive clocking network
– 700MHz primary and 325 MHz secondary
clocks
– 1GHz I/O-connected edge clocks
• Precision Clock Divider
– Phase matched x2 and x4 division of incoming clocks
• Dynamic Clock Select (DCS)
– Glitch free clock MUX
■ Masked Array for Cost Optimization
(MACO) Blocks
• On-chip structured ASIC Blocks provide preengineered IP for low power, low cost system
level integration
■ High Performance System Bus
• Ties FPGA elements together with a standard
bus framework
– Connects to peripheral user interfaces for
run-time dynamic configuration
■ System Level Support
• IEEE standard 1149.1 Boundary Scan, plus
ispTRACY internal logic analyzer
• IEEE Standard 1532 in-system configuration
• 1.2V and 1.0V operation
• Onboard oscillator for initialization and general
use
• Embedded PowerPC microprocessor interface
• Low cost wire-bond and high pin count flip-chip
packaging
• Low cost SPI Flash RAM configuration