XC2S300E-6PQG208C FPGAs Overview
Introduction
The Spartan®-IIE Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
seven-member family offers densities ranging from 50,000
to 600,000 system gates.System performance is supported beyond 200 MHz.
Features include block RAM (to 288K bits), distributed RAM
(to 221,184 bits), 19 selectable I/O standards, and four
DLLs (Delay-Locked Loops). Fast, predictable interconnect
means that successive design iterations continue to meet
timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
• Second generation ASIC replacement technology
- Densities as high as 15,552 logic cells with up to 600,000 system gates
- Streamlined features based on Virtex®-E FPGA architecture
- Unlimited in-system reprogrammability
- Very low cost
- Cost-effective 0.15 micron technology
• System level features
- SelectRAM™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K-bit true dual-port block RAM
· Fast interfaces to external RAM
- Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant
- Low-power segmented routing architecture
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
· Eliminate clock distribution delay
· Multiply, divide, or phase shift
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging
- Pb-free package options
- Low-cost packages available in all densities
- Family footprint compatibility in common packages
- 19 high-performance interface standards
· LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
· LVDS and LVPECL differential I/O
- Up to 205 differential I/O pairs that can be input,output, or bidirectional
- Hot swap I/O (CompactPCI friendly)
• Core logic powered at 1.8V and I/Os powered at 1.5V,2.5V, or 3.3V
• Fully supported by powerful Xilinx® ISE® development system
- Fully automatic mapping, placement, and routing
- Integrated with design entry and verification tools
- Extensive IP library including DSP functions and soft processors
Mark
The Xilinx Industrial components series XC2S300E-6PQG208C is 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
and you can also search for other FPGAs products.
Features
• Second generation ASIC replacement technology
- Densities as high as 15,552 logic cells with up to 600,000 system gates
- Streamlined features based on Virtex-E FPGA architecture
- Unlimited in-system reprogrammability
- Very low cost
- Cost-effective 0.15 micron technology
• System level features
- SelectRAM hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K-bit true dual-port block RAM