XC9536-15VQG44C FPGAs Overview
Description:
The XC9536-15VQG44C is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of two 36V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure2 for the architecture overview.
Features:
· 5ns pin-to-pin logic delays on all pins
· foNT to 100 MHz
·36 macrocells with 800 usable gates
· Up to 34 user I/O pins
· 5Vin-system programmable(ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
· Enhanced pin-locking architecture
· Flexible 36V18 Function Block
- 90product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals
· Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support Programmable power reduction mode in each macrocell
· Slew rate control on individual outputs· User programmable ground pin capability
· Extended pattern security features for design protection
· High-drive 24mA outputs
· 3.3 V or 5 V I/O capability
· Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently
· Available in 44-pin PLCC,44-pin VQFP, and 48-pin CSP packages
The Xilinx Embedded - CPLDs (Complex Programmable Logic Devices) series XC9536-15VQG44C is 36 MACROCELL 5 VOLT ISP CPLD (IQ AUTOMOT, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
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Features
36 macrocells with 800 usable gates
Available in small footprint package
Optimized for high-performance 2.5V systems
Low power operation
Multi-voltage operation
Advanced system features
In-system programmable
Superior pin-locking and routability with Fast CONNECT II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with individual product-term allocation
Local clock inversion with three global and one product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin inputs
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
Pin-compatible with 3.3V-core XC9536XL device in the 44-pin VQFP package